The present invention relate to a video signal processor for separating a television signal into Y (Luminance) and C (Color) signals and outputting the Y and C signals as digital video signals and, more particularly, to rate conversion of the digital video signals and generation of a clock which is used for the rate conversion.
Hereinafter, a prior art video signal processor for separating an analog television signal into Y (Luminance) and C (Color) signals, and converting the signals into digital video signals to be output is described with reference to drawings.
FIG. 9 is a block diagram illustrating the prior art video signal processor.
FIG. 10 are waveform charts of a video signal, FIG. 10(a) showing a video signal, FIG. 10(b) showing a synchronous signal, and FIG. 10(c) showing a burst signal.
FIG. 11 are diagrams for explaining the Y/C separation, FIG. 11(a) showing a video signal, FIG. 11(b) showing a Y (luminance) signal, and FIG. 11(c) showing a C (color) signal.
As shown in FIG. 9, the prior art video signal processor comprises an analog television signal input terminal 101, a first digital video signal output terminal 102, a first A/D converter circuit 103, a synchronization separator/burst detector circuit 104, a burst locked clock generator circuit 105, a Y/C separator circuit 106, a color decoder circuit 107, a TBC circuit 108, a divider circuit 112, a vertical/horizontal signal generator circuit 113, a multiplexer circuit 114, a D/A converter circuit 115, a second A/D converter circuit 116, a synchronization separator circuit 117, a horizontal synchronous clock generator circuit 118, a second digital video signal output terminal 201, a DVC preprocessing circuit 202, and a frame synchronization clock generator circuit 205.
Hereinafter, the operation of the so-constructed video signal processor is described.
The analog television signal input terminal 101 is an input terminal to which an analog television signal S101 is input. As the analog television signals, there are standard television signals which are determined by the standards like broadcasting, television signals whose synchronous signals have deviated frequencies or which include jitter, such as television signals which are reproduced for example by a video tape recorder, and non-standard television signals which are not standard television signals.
The first digital video signal output terminal 102 outputs a first digital video signal S102 which is obtained by multiplexing a Y (luminance) signal, a Cr (color difference-red) signal, Cb (color difference-blue) signal and a synchronous signal, to an apparatus or an equipment which is connected to this video signal processor, at a 27-MHz bit rate which is a transmission format of ITU-R recommendation BT.656 according to the digital interface standards.
The first A/D converter circuit 103 samples the analog television signal S101 on a 14.3-MHz burst locked clock S105 (which is described later), to be converted into a digital television signal S103. The first A/D converter circuit 103 also can sample the analog television signal S101 for example on a 28.6-MHz burst locked clock.
The synchronization separator/burst detector circuit 104 separates a synchronous signal S104a as shown in FIG. 10(b) from the digital television signal S103 as shown in FIG. 10(a) by a threshold. Further, the circuit 104 extracts a 3.58-MHz burst signal S104b as shown in FIG. 10(c), which is multiplexed as a reference signal for color reproduction, from the separated synchronous signal.
The burst locked clock generator circuit 105 multiplies the 3.58-MHz burst signal S104b by four to generate a 14.3-MHz burst locked clock S105.
The Y/C separator circuit 106 converts the digital television signal S103 in which a Y (luminance) signal and a C (color) signal are frequency-multiplexed as shown in FIG. 11(a), into a Y signal S106a as shown in FIG. 11(b) and a C signal S106b as shown in FIG. 11(c). When the input analog television signal is a standard television signal, still-picture parts are subjected to a three-dimensional processing using a frame memory, and moving-picture parts are subjected to a two-dimensional processing using a line filter, with utilizing the fact that the color phase is inverted frame/line by frame/line.
The color decoder circuit 107 demodulates the digital C signal S106 into a digital Cr signal S107a and a digital Cb signal S107b, because the phases of the Cr signal and the Cb signal are shifted by 90 degrees from each other.
The TBC (Time Base Corrector) circuit 108 detects the time of the horizontal synchronous signal of the synchronous signal S104a, and converts the Y signal S106a, the Cr signal S107a and the Cb signal S107b according to the length of the horizontal synchronous signal of the synchronous signal S104a, to be output as a Y signal S108a, a Cr signal S108b, and a Cb signal S108c. 
The D/A converter circuit 115 converts the Y signal S108a, the Cr signal S108b and the Cb signal S108c which are the digital signals output from the TBC circuit 108, into analog signals, i.e., a Y signal S115a, a Cr signal S115b, and a Cb signal S115c. 
The second A/D converter circuit 116 samples the Y signal S115a, the Cr signal S115b and the Cb signal S115c on a 13.5-MHz clock S112 (which is described later), to be converted into digital signals, i.e., a Y signal S116a, a Cr signal S116b and a Cb signal S116c. Here, it is also possible that the Cr signal and the Cb signal are multiplexed before being input to the second D/A converter circuit 115, and the D/A converter circuit 115 and the second D/A converter circuit 116 perform the conversion of the Y signal and the C signal. Further, the second A/D converter circuit also can perform the sampling for example on a 27-MHz clock.
The synchronization separator circuit 117 separates a horizontal synchronous signal S117a and a vertical synchronous signal S117b from the Y signal S116a, and outputs the signals.
The horizontal synchronous clock generator circuit 118 outputs a 27-MHz horizontal synchronous clock S118 which is synchronized with the horizontal synchronous signal S117a, to the divider circuit 112 and the multiplexer circuit 114. The horizontal synchronous clock generator circuit 118 is commonly constituted by an analog PLL circuit.
The divider circuit 112 divides the frequency of the 27-MHz horizontal synchronous clock S118 into 13.5 MHz. This 13.5-MHz clock S112 is the above-mentioned sampling clock which is input into the second A/D converter circuit 116.
The vertical/horizontal signal generator circuit 113 generates a synchronous signal S113 corresponding to a BT.656 transmission format, from the horizontal synchronous signal S117a and the vertical synchronous signal S117b, and output the signal S113.
The multiplexer circuit 114 multiplexes the Y signal S116a, the Cr signal S116b, the Cb signal S116c and the synchronous signal S113 on the 27-MHz horizontal synchronous clock S118, and outputs a multiplexed signal as the first digital video signal S102. The first digital video signal S102 is output from the first digital video signal output terminal 102 to an apparatus or an equipment which is connected to this video signal processor.
The second digital video signal output terminal 201 is an output terminal for outputting a second digital video signal S201 in which the Y signal, the Cr signal and the Cb signal are multiplexed, at 18 MHz. The second digital video signal S201 is input to a DCT (Discrete Cosine Transform) block for performing intra-frame compression/decompression, processed at 18 MHz, and thereafter recorded/reproduced by a block for performing recording/reproduction into/from a tape.
The DVC preprocessing circuit 202 multiplexes the 13.5-MHz Y signal S116a, Cr signal S116a and Cb signal S116c which are output from the second A/D converter circuit 116, on the basis of a 18-MHz clock S205 which is synchronized with one frame (described later), to be output as the second digital video signal S201. At this time, the DVC preprocessing circuit 202 decompresses the Y signal S116a into a 18-MHz Y signal, thins down the Cr signal S116b and the Cb signal S116c into 9 MHz, and thereafter multiplexes these signals.
The frame synchronization clock generator circuit 205 generates and outputs the 18-MHz clock S205 which is synchronized with one frame, corresponding to twice of the vertical synchronous signal S117b which is output from the synchronization separator circuit 117. Here, the frame synchronous clock generator circuit 205 is commonly constituted by an analog PLL circuit.
However, in the prior art video signal processor, in order to convert the rates of the 14.3-MHz digital Y signal, digital Cr signal and digital Cb signal to obtain the 13.5-MHz digital Y signal, digital Cr signal and digital Cb signal, it is required to provide an external analog PLL circuit, like the horizontal synchronous clock generator circuit 118 for generating the 27-MHz horizontal synchronous clock S118. Further, also when the 13.5-MHz digital Y signal, digital Cr signal and digital Cb signal are subjected to the rate conversion to obtain the 18-MHz digital Y signal, digital Cr signal and digital Cb signal, and then these signals are multiplexed, an analog PLL circuit like the frame synchronization clock generator circuit 205 for generating the 18-MHz clock S205 is required.
As described above, in the prior art video signal processor, it is required to provide an external analog PLL circuit to perform the rate conversion of the digital video signals, whereby the circuit (component) scale is increased and the integration of the LSI becomes difficult.
Therefore, the present invention has an object to provide a video signal processor and a video signal processing method, which reduces the circuit scale as well as facilitates the integration of the LSI.
A sampling frequency converter according to one aspect of the present invention comprises: a digital-digital conversion means for receiving a first digital video signal which has been sampled on a first clock signal having a first frequency, interpolating the first digital video signal to calculate a second digital video signal, a length of one horizontal period and a sampling frequency of which signal are the same as those of the first digital video signal and an effective pixel period in one horizontal period of which signal is N times (N greater than 0) as long as that of the first digital video signal, and converting the first digital video signal into the second digital video signal to be output on the basis of the first clock signal; a clock generation means for generating a second clock signal having a second frequency which is one-Nth as high as that of the first clock signal; and a storage means for retaining the second digital video signal as well as reading the retained second digital video signal on the second clock signal to be output as a third digital video signal.
According to the sampling frequency converter of the above-discussed aspect of the present invention, the rate conversion of the digital video signal is enabled without providing an analog PLL circuit for generating a clock which is synchronized with a horizontal synchronous signal.
A video signal processor according to another aspect of the present invention comprises: an A/D converter circuit for sampling an analog video signal on a first clock signal having a first frequency, to be converted into a first digital video signal; a synchronous signal separation means for separating a first synchronous signal from the analog video signal; a first clock generation means for generating the first clock signal from the first synchronous signal; and a sampling frequency converter for interpolating the first digital video signal to be converted into a second digital video signal, and outputting the second digital video signal on the basis of a second clock signal having a second frequency. The sampling frequency converter comprises: a first digital-digital conversionmeans for interpolating the first digital video signal to calculate a second digital video signal, a length of one horizontal period and a sampling frequency of which signal are the same as those of the first digital video signal and an effective pixel period in one horizontal period of which signal is N times (N greater than 0) as long as that of the first digital video signal, and converting the first digital video signal into the second digital video signal to be output on the basis of the first clock signal; a second clock generation means for generating a second clock signal having a second frequency which is one-Nth as high as that of the first clock signal; and a storage means for retaining the second digital video signal as well as reading the retained second digital video signal on the second clock signal to be output as a third digital video signal.
According to the video signal processor of the above-discussed aspect of the present invention, the rate conversion of the digital video signal is enabled without providing outside an analog PLL circuit for generating a clock which is synchronized with a horizontal synchronous signal, whereby the circuit scale is reduced and the integration of the LSI is easily performed.
According to a video signal processor of another aspect of the present invention, a video signal processor discussed above further comprises: a multiplication means for multiplying the second clock signal to generate a third clock signal having a third frequency; a division means for dividing the third clock signal to generate a fourth clock signal having a fourth frequency; and a second digital-digital conversion means for converting the third digital video signal into a fourth digital video signal on the basis of the fourth clock signal.
According to the video signal processor of the above-discussed aspect of the present invention, the rate conversion of the digital video signal is enabled without providing outside an analog PLL circuit for generating a clock which is synchronized with one frame, whereby the circuit scale is reduced and the integration of the LSI is easily performed.
According to the video signal processor of another aspect of the present invention, the video signal processor of an above-discussed aspect further comprises a synchronization comparison means for comparing a phase of the first synchronous signal with a phase of a second synchronous signal which is generated from the second clock signal. The storage means comprises: a first frame storage means for retaining the second digital video signal in frame units as well as reading the retained second digital video signal in frame units on the basis of the second clock signal to be output as a fourth digital video signal; a second frame storage means for retaining the second digital video signal in frame units as well as reading the retained second digital video signal in frame units on the basis of the second clock signal to be output as a fifth digital video signal; and a switching means for receiving the fourth digital video signal and the fifth digital video signal, and alternately switching between the fourth digital video signal and the fifth digital video signal to be output as the third digital video signal. The synchronous comparison means outputs a switch signal which instructs the switching means to output either the fourth digital video signal or fifth digital video signal as the third digital video signal repeatedly twice when it detects that the phase of the first synchronous signal has gotten ahead of the phase of the second synchronous signal, and outputs a switch signal which instructs the switching means to eliminate one frame of either the fourth digital video signal or fifth digital video signal when it detects that the phase of the second synchronous signal has gotten ahead of the phase of the first synchronous signal, to the switching means, and the switching means outputs one of the fourth digital video signal and the fifth digital video signal as the third digital video signal, in accordance with the switch signal.
According to the video signal processor of the above-discussed aspect of the present invention, the occurrence of noises on a screen can be avoided even when non-standard television signals are input.
A sampling frequency conversion method according to another aspect of the present invention comprises: a digital-digital conversion step of receiving a first digital video signal which has been sampled on a first clock signal having a first frequency, interpolating the first digital video signal to calculate a second digital video signal, a length of one horizontal period and a sampling frequency of which signal are the same as those of the first digital video signal and an effective pixel period in one horizontal period of which signal is N times (N greater than 0) as long as that of the first digital video signal, and converting the first digital video signal into the second digital video signal to be output on the basis of the first clock signal; a clock generation step of generating a second clock signal having a second frequency which is one-Nth as high as that of the first clock signal; and a storage step of retaining the second digital video signal as well as reading the retained second digital video signal on the second clock signal to be output as a third digital video signal.
According to the sampling frequency conversion method of the above-discussed aspect of the present invention, the sampling frequency converter which enables the rate conversion of the digital video signal can be constituted, without providing an analog PLL circuit for generating a clock which is synchronized with a horizontal synchronous signal.
A video signal processing method according to another aspect of the present invention comprises: an A/D conversion step of sampling an analog video signal on a first clock signal having a first frequency to be converted into a first digital video signal; a synchronous signal separation step of separating a first synchronous signal from the analog video signal; a first clock generation step of generating the first clock signal from the first synchronous signal; a first digital-digital conversion step of interpolating the first digital video signal to calculate a second digital video signal, a length of one horizontal period and a sampling frequency of which signal are the same as those of the first digital video signal and an effective pixel period in one horizontal period of which signal is N times (N greater than 0) as long as that of the first digital video signal, and converting the first digital video signal into the second digital video signal to be output on the basis of the first clock signal; a second clock generation step of generating a second clock signal having a second frequency which is one-Nth as high as that of the first clock signal; and a storage step of retaining the second digital video signal as well as reading the retained second digital video signal on the second clock signal to be output as a third digital video signal.
According to the video signal processing method of the above-discussed aspect of the present invention, the video signal processor which can perform the rate conversion of the digital video signal without providing outside an analog PLL circuit for generating a clock which is synchronized with a horizontal synchronous signal, has a reduced circuit scale, and easily performs the integration of the LSI can be constituted.
According to the video signal processing method of another aspect of the present invention, the video signal processing method of the above-discussed aspect further comprises: a multiplication step of multiplying the second clock signal to generate a third clock signal having a third frequency; a division step of dividing the third clock signal to generate a fourth clock signal having a fourth frequency; and a second digital-digital conversion step of converting the third digital video signal into a fourth digital video signal on the basis of the fourth clock signal.
According to the video signal processing method of the above-discussed aspect of the present invention, the rate conversion of the digital video signal is enabled without providing outside an analog PLL circuit for generating a clock which is synchronized with one frame, whereby the circuit scale is reduced and the integration of the LSI is easily performed.
According to the video signal processing method of another aspect of the present invention, the video signal processing method of an above-discussed aspect further comprises a synchronization comparison step of comparing a phase of the first synchronous signal with a phase of a second synchronous signal which is generated from the second clock signal. The storage step comprises: a first frame storage step of retaining the second digital video signal in frame units as well as reading the retained second digital video signal on the basis of the second clock signal in frame units to be output as a fourth digital video signal; a second frame storage step of retaining the second digital video signal in frame units as well as reading the retained second digital video signal on the basis of the second clock signal in frame units to be output as a fifth digital video signal; and a switching step of receiving the fourth digital video signal and the fifth digital video signal, and alternately switching between the fourth digital video signal and the fifth digital video signal to be output as the third digital video signal. The synchronization comparison step outputs a switch signal which instructs to output either the fourth digital video signal or the fifth digital video signal as the third digital video signal repeatedly twice when it is detected that the phase of the first synchronous signal has gotten ahead of the phase of the second synchronous signal, and outputs a switch signal which instructs to eliminate one frame of either the fourth digital video signal or fifth digital video signal when it is detected that the phase of the second synchronous signal has gotten ahead of the phase of the first synchronous signal. The switching step outputs one of the fourth digital video signal and the fifth digital video signal as the third digital video signal, in accordance with the switch signal.
According to the video signal processing method of the above-discussed aspect of the present invention, the occurrence of noises on a screen can be prevented even when non-standard television signal are input.